ESSI Programming Model
7.5.10 Receive Slot Mask Registers (RSMA, RSMB)
Both receive slot mask registers are read/write registers. In Network mode, the receiver(s) use
these registers to determine which action to take in the current time slot. Depending on the setting
of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive a data word and
generate a receiver full condition.
23
22
21
20
19
18
17
16
15
14
13
12
RS15
RS14
RS13
RS12
11
RS11
10
RS10
9
RS9
8
RS8
7
RS7
6
RS6
5
RS5
4
RS4
3
RS3
2
RS2
1
RS1
0
RS0
—Reserved bit; read as 0; write to 0 0 for future compatibility.
(ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2)
Figure 7-16. ESSI Receive Slot Mask Register A (RSMA)
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
11
RS27
10
RS26
9
RS25
8
RS24
7
RS23
6
RS22
5
RS21
4
RS20
3
RS19
2
RS18
1
RS17
0
RS16
–Reserved. Read as zero. Write with zero for future compatibility.
(ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)
Figure 7-17. ESSI Receive Slot Mask Register B (RSMB)
RSMA and RSMB (as in Figure 7-12 and Figure 7-13 ) can be seen as one 32-bit register, RSM.
Bit n in RSM (RSn) is an enable/disable control bit for time slot number N. When RSn is cleared,
all the data signals of the enabled receivers are tri-stated during time slot number N. Data
transfers from the receive data register(s) to the receive shift register(s), but the RDF and ROE
flags are not set. Consequently, during a disabled slot, no receiver full interrupt is generated. The
DSP is interrupted only for enabled slots. When RSn is set, the receive sequence proceeds
normally. Data is received during slot number N, and the RDF flag is set.
When the bits in the RSMx are set, the frame being transmitted is unaffected, but the next frame
transmission is affected. If the RSMx is read, it shows the current setting. When the internal data
bus reads RSMA or RSMB, the register contents occupy the two low-order bytes of the data bus,
and the high-order byte is filled by 0.
After a hardware RESET signal or a software RESET instruction, the RSM register is reset to
$FFFFFFFF, enabling all 32 time slots for data transmission.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
7-33
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